ISTOK VA STOK SOHALARINI ZATVOR OSTI OKSID BILAN QOPLANISH DARAJASINI MAYDONIY TRANZISTORLARNING QIZISH TEMPERATURASIGA TA’SIRI

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Xidoyat Abdikarimov

Annotatsiya

Annotatsiya. Ushbu maqolada Sentaurus TCAD dasturi yordamida 3D o‘lchovli modellashtirish orqali kanal ko‘ndalang kesim yuzasi doira va kvadrat bo‘lgan nano o‘lchamdagi zatvor bilan to‘liq o‘ralgan maydoniy tranzistorni qizish temperaturasiga istok va stok sohalarini zatvor osti oksid bilan qoplanib borish darajasining ta’siri o‘rganilgan.

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Bo‘lim
Fizika

Foydalaniladigan adabiyotlar

Moore More: International Roadmap for Devices and Systems (IRDS).

https://irds.ieee.org/images/files/pdf/2017/2017IRDS_ES.pdf, 2017 (Accessed 09

March 2021).

Kim, Y-B., Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics, Trans. On Electronics and Electronic materials 11 (2010) 93-105.

https://doi.org/10.4313/TEEM.2010.11.3.093.

Colinge, J. P., Multiple-gate SOI MOSFETs, Solid-state Electronics 48 (2004) 897-905. https://doi.org/10.1016/j.sse.2003.12.020.

Colinge, J. P., Multiple-gate SOI MOSFETs, Microelectronics Engineering 84 (2007) 2071-2076. https://doi.org/10.1016/j.mee.2007.04.038.

Colinge, J. P., FinFET and other multi-gate transistors, In New York: Springer-Verlag. ISBN 978-0-387-71751-7

Jimenez, D., Jimenez, J. J. Saenz, Iniguez, B., Sune, J., Marsal, L. F., Pallares, J., Modeling nanoscale gate-all-around MOSFETs, IEEE Electron Device Letter 25(5) (2004) 314-316. https://doi.org/10.1109/LED.2004.826526.

S. Bangsaruntip, “Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond,” in Proc. IEEE Electron Devices Meeting (IEDM), Washington, DC, USA, Dec. 2013, pp. 20.2.1–20.2.4